This invention relates to gate-source structures for static induction transistors and, in particular, to a recessed gate structure which improves device performance and which requires relatively simple fabrication techniques.
The static induction transistor is a field effect semiconductor device capable of operation at relatively high frequency and power. The transistors are characterized by a short, high resistivity semiconductor channel which may be controllably depleted of carriers. The current-voltage characteristics of the static induction transistor are generally similar to those of a vacuum tube triode. The devices are described by Nishizawa et al in U.S. Pat. No. 3,828,230 issued Aug. 6, 1974.
The static induction transistor generally uses a vertical geometry with source and drain electrodes placed on opposite sides of a thin, high resistivity layer of one conductivity type. Gate regions of the opposite conductivity type are positioned in the high resistivity layer on opposite sides of the source. During operation a reverse bias is applied between the gate region and the remainder of the high resistivity layer causing a depletion region to extend into the channel below the source. As the magnitude of the reverse bias voltage is varied, the source-drain current and voltage derived from an attached energy source will also vary.
The design and fabrication of the gate-source structure of vertical geometry static induction transistors is difficult. In general, the manufacture of the devices has utilized two basic geometries. One of these geometries calls for placement of the gate junctions on the same surface of the device as source electrodes. The other geometry calls for burying of the gate junctions within the high resistivity semiconductor material between the source and drain electrodes.
The surface-gate geometry facilitates manufacture and results in superior high frequency capability because of its relatively low gate capacitance. However, the surface location of the gate regions adjacent to the source electrode causes inherent difficulty in extending the depletion region under the source and into the channel between the source and drain. In general, the gate regions are of limited depth because of limitations associated with diffusion processes. Because of the limited depth of the gate regions, a relatively large reverse bias voltage must be applied to the gate electrode to deplete the carriers in the channel under the source electrode. Therefore, the surface-gate geometry devices generally have low voltage gain.
The buried-gate structure, on the other hand, is relatively difficult to manufacture but, because of the proximity of the gate regions to the channel, has a high voltage gain. Present buried-gate-structure devices are limited to relatively low frequency operation because of large gate capacitance and resistance.
Previously proposed geometries which combine the low capacitance of the surface-gate structure with the high voltage gain of the buried-gate structure call for extending the gate region below the source and closer to the channel by first etching a relatively deep slot or groove into the surface on each side of the source. The gate region is then formed by one of two methods. One method involves epitaxially refilling each slot or groove to form the gate region. The other method involves diffusion of the gate region into the semiconductor material surrounding each slot or groove.
Both methods require relatively complicated manufacturing processes and neither method fully combines the advantages of the two basic gate structures. While the voltage gain resulting from both methods is high, the resulting gate capacitance is large. A particular problem resulting from use of the diffusion method is the fact that the unprotected vertical side walls of the slot or groove represent a contamination window during device operation.